1. Field of the Invention
This invention relates to a multiple virtual storage system, and more particularly to an address control apparatus for providing a segment table designation needed when a program being executed accesses a plurality of virtual address spaces concurrently, at high speed with good efficiency.
2. Description of the Related Art
Heretofore, in multiple virtual storage systems, a virtual address space possessing an instruction to be executed and the associated operand is determined according to segment and page tables located on a main storage, and each virtual address space is referred to by a pointer which is called a segment table designation (STD) positioning the segment table located on the main storage. This STD is prestored in a predetermined control register in a processor.
The technical concept that a program being executed performs concurrent accessing to a plurality of address spaces is exemplified by Japanese Patent Laid-Open Publication No. 140576/1981. According to this prior concept, access registers (ARs) related to general registers (GRs) are located in a processor, and the STD directly designating a virtual address space possessing an operand is stored in each of the ARs. Using the STD in the AR related to the GR to be used as a base register during the operand access, a virtual address space of the operand is designated so that a program being executed can access a plurality of address spaces concurrently.
This prior art merely discloses the ARs directly storing the STD but is totally silent about any address control system in which the content of an AR indirectly designates an STD.
Specifically, the STD which designates a virtual address space accessible from an instruction being executed is prepared on a main storage as a table by a system program. And a leading address of the table as well as an address in the table, which are given from the system program, are held in a control register (CR) and an AR, respectively. With the system in which the CR and AR designate the STD indirectly, the STD cannot be obtained until the contents of the CR and AR are added at every operand access whereupon reference must be made, with the resulting address, to the table on the main storage. As a consequence, its overhead would increase to lower the processing performance
The more complex the translating process before making reference to the table storing the STDs, the further the processing performance is lowered.